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rt7275/76 ? ds7275/76-00 january 2013 www.richtek.com 1 ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. 3a, 18v, 700khz acot tm synchronous step-down converter simplified application circuit general description the rt7275/76 are high-performance 700khz 3a step- down regulators with internal power switches and synchronous rectifiers. they feature quick transient response using their advanced constant on-time (acot tm ) control architecture that provides stable operation with small ceramic output capacitors and without complicated external compensation, among other benefits. the input voltage range is from 4.5v to 18v and the output is adjustable from 0.765v to 8v. the proprietary acot tm control improves upon other fast- response constant on-time architectures, achieving nearly constant switching frequency over line, load, and output voltage ranges. since there is no internal clock, response to transients is nearly instantaneous and inductor current can ramp quickly to maintain output regulation without large bulk output capacitance. the rt7275/76 are stable with and optimized for ceramic output capacitors. with internal 90m switches and 60m synchronous rectifiers, the rt7275/76 display excellent efficiency and good behavior across a range of applications, especially for low output voltages and low duty cycles. cycle-by- cycle current limit, input under-voltage lock-out, externally-adjustable soft-start, output under- and over- voltage protection, and thermal shutdown provide safe and smooth operation in all operating conditions. the rt7275 and RT7276 are each available in wdfn-10l 3x3 and ptssop-14 packages, with exposed thermal pads. rt7275/76 pvcc vin v in ss v out en input signal pgood power good boot sw fb vout vinr pgnd gnd features z z z z z fast transient response z z z z z steady 700khz switching frequency ` ` ` ` ` at all load currents (rt7275) ` ` ` ` ` discontinuous operating mode at light load (RT7276) z z z z z 3a output current z z z z z advanced constant on-time (acot tm ) control z z z z z optimized for ceramic output capacitors z z z z z 4.5v to 18v input voltage range z z z z z internal 90m switch and 60m synchronous rectifier z z z z z 0.765v to 8v adjustable output voltage z z z z z externally-adjustable, pre-biased compatible soft- start z z z z z cycle-by-cycle current limit z z z z z optional output discharge function (ptssop-14 only) z z z z z output over- and under-voltage shut-down applications z industrial and commercial low power systems z computer peripherals z lcd monitors and tvs z green electronics/appliances z point of load regulation for high-performance dsps, fpgas, and asics z not recommended for sink/source applications fast-transient response v out = 12v, v out = 1.05v, i out = 0 to 3a time (100 s/div) i out (2a/div) v out (20mv/div) rt7275 free datasheet http:///
rt7275/76 2 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. marking information ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) tssop-14 (exposed pad) wdfn-10l 3x3 fb vin pgnd gnd ss pvcc pgood en pgnd sw sw boot vout vinr 4 2 3 5 7 6 11 13 12 10 8 9 14 pgnd 15 en fb pgood ss vin vin boot sw sw pvcc 9 8 7 9 1 2 3 4 5 10 pgnd 11 RT7276 gcpymdnn RT7276gcp : product number ymdnn : date code 2c= : product code ymdnn : date code RT7276gcp RT7276gqw 2c=ym dnn rt7275gcp : product number ymdnn : date code rt7275gcp rt7275gqw 4c= : product code ymdnn : date code rt7275 gcpymdnn 4c=ym dnn rt7275/76 package type cp : tssop-14 (exposed pad) qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free) operating mode 75 : continuous switching mode 76 : discontinuous operating mode at light load free datasheet http:///
rt7275/76 3 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. (v in = 12v, t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) z supply input voltage, vin --------------------------------------------------------------------------------------- 4.5v to 18v z junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, vin, vin r (tssop-14 (exposed pad)) ----------------------------------------- ? 0.3v to 21v z switch node, sw ------------------------------------------------------------------------------------------------- ? 0.8v to (v vin + 0.3v) z switch node, sw (<10ns) --------------------------------------------------------------------------------------- ? 5v to 25v z boot to sw ------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z pvcc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z pvcc to vin (wdfn-10l 3x3) or vinr (tssop-14 (exposed pa d)) --------------------------------- ? 18v to 0.3v z other pins ----------------------------------------------------------------------------------------------------------- ? 0.3v to 21v z power dissipation, p d @ t a = 25 c tssop-14 (exposed pad) -------------------------------------------------------------------------------------- 2.50w wdfn-10l 3x3 ----------------------------------------------------------------------------------------------------- 1.67w z package thermal resistance (note 2) tssop-14 (exposed pad), ja -------------------------------------------------------------------------------- 40 c/w wdfn-10l 3x3, ja ----------------------------------------------------------------------------------------------- 60 c/w wdfn-10l 3x3, jc ----------------------------------------------------------------------------------------------- 7.5 c/w z junction temperature range ------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) ---------------- ------------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) -------------------------------------------------------------------------------------- 2kv parameter symbol test conditions min typ max unit supply current supply current (shutdown) v en = 0v -- 1 10 a supply current (quiescent) v en = 3v, v fb = 1v -- 0.7 -- ma logic threshold logic high v ih 2 -- -- en voltage logic low v il -- -- 0.4 v v fb voltage and discharge resistance feedback threshold voltage v fb_th 4.5v v in 18v 0.757 0.765 0.773 v feedback input current i fb v fb = 0.8v ? 0.1 0 0.1 a vout discharge resistance r dis v en = 0v, v vout = 0.5v -- 50 100 pvcc output pvcc output voltage v pvcc 6v v in 18v, 0 < i pvcc < 5ma 4.7 5.1 5.5 v pvcc line regulation 6v v in 18v, i pvcc = 5ma -- -- 20 mv free datasheet http:///
rt7275/76 4 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. the pcb copper area of exposed pad is 70mm 2 . note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit pvcc load regulation 0 < i pvcc < 50ma -- -- 40 mv output current i pvcc v in = 6v, v pvcc = 4v -- 110 -- ma on-resistance (r ds(on) ) high side r ds(on) _h for wdfn-10l 3x3 -- 90 -- high side r ds(on) _h for tssop-14 (exposed pad) -- 100 -- switch on resistance low side r ds(on) _l -- 60 -- m current limit (upper threshold) i lim l sw = 1.4 h 3.5 4.5 5.7 a thermal shutdown thermal shutdown threshold t sd -- 150 -- c thermal shutdown hysteresis t sd -- 20 -- c on-time and off-time control on-time t on v in = 12v, v out = 1.05v -- 145 -- ns minimum on-time t on(min) -- 60 -- ns minimum off-time t off(min) -- 230 -- ns soft-start ss charge current v ss = 0v 1.4 2 2.6 a ss discharge current v ss = 0.5v 0.05 0.1 -- ma vin uvlo v vin / v vinr rising, enable pvcc regulator 3.55 3.85 4.15 uvlo threshold threshold hysteresis -- 0.3 -- v power good v fb rising 85 90 95 pgood threshold v fb falling -- 85 -- % pgood sink current pgood = 0.5v -- 5 -- ma output under voltage and over voltage protection ovp trip threshold v fb rising 115 120 125 % ovp delay time -- 5 -- s v fb falling 65 70 75 uvp trip threshold hysteresis -- 10 -- % uvp delay time -- 250 -- s free datasheet http:///
rt7275/76 5 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 12v rt7275 v out = 5v v out = 2.5v v out = 1.05v typical operating characteristics switching frequency vs. output current 0 100 200 300 400 500 600 700 800 900 0 0.5 1 1.5 2 2.5 3 output current (a) switching frequency (khz) 1 v out = 1.05v RT7276 v in = 5v v in = 12v v in = 17v output voltage vs. load current 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 00.511.522.53 load current (a) output voltage (v) v out = 1.05v v in = 17v v in = 12v v in = 5v RT7276 output voltage vs. load current 1.038 1.040 1.042 1.044 1.046 1.048 0 0.5 1 1.5 2 2.5 3 load current (a) output voltage (v) v in = 17v v in = 12v v in = 5v v out = 1.05v rt7275 switching frequency vs. load current 600 650 700 750 800 00.511.522.53 output current (a) switching frequency (khz) 1 v in = 17v v in = 12v v in = 5v v out = 1.05v rt7275 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) RT7276 v in = 12v v out = 5v v out = 2.5v v out = 1.05v free datasheet http:///
rt7275/76 6 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. quiescent current vs. temperature 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 -50-25 0 25 50 75100125 temperature (c) quiescent current (ma ) rt7275 shutdown current vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50-25 0 25 50 75100125 temperature (c) shutdown current (a) 1 v out = 1.05v v in = 17v v in = 12v v in = 5v v out = 1.05v v in = 5v v in = 17v v in = 12v quiescent current vs. temperature 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 -50 -25 0 25 50 75 100 125 temperature (c) quiescent current (ma ) RT7276 v in = 5v v in = 17v v in = 12v v out = 1.05v feedback voltage v s. input voltage 0.750 0.755 0.760 0.765 0.770 4681012141618 input voltage (v) feedback voltage (v) i out = 0.1a feedback voltage vs. temperature 0.750 0.755 0.760 0.765 0.770 -50 -25 0 25 50 75 100 125 temperature (c) feedback voltage (v) v in = 17v v in = 12v v in = 5v v out = 1.05v, i out = 0a en current vs. en voltage 0 1 2 3 4 0 2 4 6 8 1012141618 en voltage (v) en current (a) v in = 12v, v out = 1.05v free datasheet http:///
rt7275/76 7 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. maximum output current vs. temperature 3.5 3.9 4.3 4.7 5.1 5.5 -50 -25 0 25 50 75 100 125 temperature (c) maximum output current (a) 1 v in = 5v v in = 17v v in = 12v v out = 0v pvcc output voltage vs. output current 5.00 5.05 5.10 5.15 5.20 020406080100 pvcc output current (ma) pvcc output voltage (v) v in = 12v pvcc output voltage vs. input voltage 5.00 5.05 5.10 5.15 5.20 5 7 9 11131517 input voltage (v) pvcc output voltage (v) no load 5ma load v in = 12v, i out = 5ma v out = 12v, v out = 1.05v, i out = 1a to 3a time (100 s/div) load transient response i out (2a/div) v out (20mv/div) v out = 12v, v out = 1.05v, i out = 0 to 3a time (100 s/div) load transient response i out (2a/div) v out (20mv/div) rt7275 rt7275/RT7276 current limit thresholds vs. input voltage 3.0 3.5 4.0 4.5 5.0 5.5 5 7 9 11131517 input voltage (v) current limit thresholds (a ) upper threshold lower threshold v out = 0v free datasheet http:///
rt7275/76 8 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (4ms/div) power off from vin v in = 12v, v out = 1.05v, i out = 3a v out (1v/div) v sw (10v/div) i out (2a/div) v in (20v/div) time (4ms/div) power on from en v out (1v/div) v sw (10v/div) i out (2a/div) v en (10v/div) v in = 12v, v out = 1.05v, i out = 3a v in = 12v, v out = 1.05v, i out = 3a time (400ns/div) output ripple voltage v out (10mv/div) v sw (10v/div) v in = 12v, v out = 1.05v, i out = 3a time (4ms/div) power on from vin v out (1v/div) v sw (10v/div) i out (2a/div) v in (20v/div) time (100 s/div) power off from en v out (1v/div) v sw (10v/div) i out (2a/div) v en (10v/div) v in = 12v, v out = 1.05v, i out = 3a free datasheet http:///
rt7275/76 9 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. tssop-14 (exposed pad) wdfn-10l 3x3 pin name pin function 1 -- vout optional output voltage discharge connection. this open drain output connects to ground when the device is disabled. if output voltage discharge is desired, connect vout to the output voltage. 2 2 fb feedback input voltage. connect fb to the midpoint of the external feedback resistive divider to sense the output voltage. place the resistive divider within 5mm from the fb pin. the ic regulates v fb at 0.765v (typical). 3 3 pvcc linear regulator output. pvcc is the output of the internal 5.1v linear regulator powered by vin (wdfn-10l 3x3) or vinr (tssop-14 (exposed pad)). connect a 1 f ceramic capacitor from pvcc to ground. 4 4 ss soft-start control. connect an external capacitor between this pin and ground to set the soft-start time. 5 -- gnd analog ground. 6 5 pgood open drain power-good output. pgood connects to pgnd whenever v fb is less than 90% of its regulation threshold (typical). 7 1 en enable control input. connect en to a logic-high voltage to enable the ic or to a logic-low voltage to disable. do not leave this high impedance input unconnected. 8, 9, 15 (exposed pad) 11 (exposed pad) pgnd power ground. pgnd connects to the source of the internal n-channel mosfet synchronous rectifier and to other power ground nodes of the ic. the exposed pad and the 2 pgnd pins (tssop-14 (exposed pad)) should be well soldered to the input and output capacitors and to a large pcb area for good power dissipation. 10, 11 6, 7 sw switching node. sw is the source of the internal n-channel mosfet switch and the drain of the internal n-channel mosfet synchronous rectifier. connect sw to the inductor with a wide short pcb trace and minimize its area to reduce emi. 12 8 boot bootstrap supply for high side gate driver. connect a 0.1 f capacitor between boot and sw to power the internal gate driver. 13 9, 10 vin power input. vin is the drain of the internal n-channel mosfet switch. connect vin to the input capacitor. for the wdfn-10l 3x3 package, vin also supplies power to the internal linear regulator. 14 -- vinr internal linear regulator supply input. for the tssop-14 (exposed pad) package, vinr supplies power for the internal linear regulator that powers the ic. connect vin to the input voltage and bypass to ground with a 0.1 f ceramic capacitor. functional pin description free datasheet http:///
rt7275/76 10 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram detailed description the rt7275/76 are high-performance 700khz 3a step- down regulators with internal power switches and synchronous rectifiers. they feature an advanced constant on-time (acot tm ) control architecture that provides stable operation with ceramic output capacitors without complicated external compensation, among other benefits. the input voltage range is from 4.5v to 18v and the output is adjustable from 0.765v to 8v. the proprietary acot tm control scheme improves upon other constant on-time architectures, achieving nearly constant switching frequency over line, load, and output voltage ranges. the rt7275/76 are optimized for ceramic output capacitors. since there is no internal clock, response to transients is nearly instantaneous and inductor current can ramp quickly to maintain output regulation without large bulk output capacitance. constant on-time (cot) control the heart of any cot architecture is the on-time one- shot. each on-time is a pre-determined ? fixed ? period that is triggered by a feedback comparator. this robust arrangement has high noise immunity and is ideal for low duty cycle applications. after the on-time one-shot period, there is a minimum off-time period before any further regulation decisions can be considered. this arrangement avoids the need to make any decisions during the noisy time periods just after switching events, when the switching node (sw) rises or falls. because there is no fixed clock, the high-side switch can turn on almost immediately after load transients and further switching pulses can ramp the inductor current higher to meet load requirements with minimal delays. traditional current mode or voltage mode control schemes typically must monitor the feedback voltage, current signals (also for current limit), and internal ramps and compensation signals, to determine when to turn off the high-side switch and turn on the synchronous rectifier. weighing these small signals in a switching environment is difficult to do just after switching large currents, making those architectures problematic at low duty cycles and in less than ideal board layouts. ugate lgate driver sw boot pvcc switch controller on-time over current protection en fb comparator sw pgnd internal regulator vbias v ref vinr tssop-14 (exposed pad) gnd tssop-14 (exposed pad) pvcc under & over voltage protection fb 0.9 v ref + - pgood + - - 2a pvcc ripple gen. vin en vout tssop-14 (exposed pad) discharge fb pgood comparator ss vin (wdfn-10l 3x3) free datasheet http:///
rt7275/76 11 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. because no switching decisions are made during noisy time periods, cot architectures are preferable in low duty cycle and noisy applications. however, traditional cot control schemes suffer from some disadvantages that preclude their use in many cases. many applications require a known switching frequency range to avoid interference with other sensitive circuitry. true constant on-time control, where the on-time is actually fixed, exhibits variable switching frequency. in a step-down converter, the duty factor is proportional to the output voltage and inversely proportional to the input voltage. therefore, if the on-time is fixed, the off-time (and therefore the frequency) must change in response to changes in input or output voltage. modern pseudo-fixed frequency cot architectures greatly improve cot by making the one-shot on-time proportional to v out and inversely proportional to v in . in this way, an on-time is chosen as approximately what it would be for an ideal fixed-frequency pwm in similar input/output voltage conditions. the result is a big improvement but the switching frequency still varies considerably over line and load due to losses in the switches and inductor and other parasitic effects. another problem with many cot architectures is their dependence on adequate esr in the output capacitor, making it difficult to use highly-desirable, small, low-cost, but low-esr ceramic capacitors. most cot architectures use ac current information from the output capacitor, generated by the inductor current passing through the esr, to function in a way like a current mode control system. with ceramic capacitors the inductor current information is too small to keep the control loop stable, like a current mode system with no current information. acot tm control architecture making the on-time proportional to v out and inversely proportional to v in is not sufficient to achieve good constant-frequency behavior for several reasons. first, voltage drops across the mosfet switches and inductor cause the effective input voltage to be less than the measured input voltage and the effective output voltage to be greater than the measured output voltage. as the load changes, the switch voltage drops change causing a switching frequency variation with load current. also, at light loads if the inductor current goes negative, the switch dead-time between the synchronous rectifier turn-off and the high-side switch turn-on allows the switching node to rise to the input voltage. this increases the effective on- time and causes the switching frequency to drop noticeably. one way to reduce these effects is to measure the actual switching frequency and compare it to the desired range. this has the added benefit eliminating the need to sense the actual output voltage, potentially saving one pin connection. acot tm uses this method, measuring the actual switching frequency and modifying the on-time with a feedback loop to keep the average switching frequency in the desired range. to achieve good stability with low-esr ceramic capacitors, acot tm uses a virtual inductor current ramp generated inside the ic. this internal ramp signal replaces the esr ramp normally provided by the output capacitor's esr. the ramp signal and other internal compensations are optimized for low-esr ceramic output capacitors. acot tm one-shot operation the rt7275/76 control algorithm is simple to understand. the feedback voltage, with the virtual inductor current ramp added, is compared to the reference voltage. when the combined signal is less than the reference the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. the on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. after the on- time, the high-side switch is turned off and the synchronous rectifier is turned on and the inductor current ramps down linearly. at the same time, the minimum off-time one-shot is triggered to prevent another immediate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. the minimum off-time is kept short (230ns typical) so that rapidly-repeated on- times can raise the inductor current quickly when needed. free datasheet http:///
rt7275/76 12 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. discontinuous operating mode (RT7276 only) after soft start, the rt7275 operates in fixed frequency mode to minimize interference and noise problems. the RT7276 uses variable-frequency discontinuous switching at light loads to improve efficiency. during discontinuous switching, the on-time is immediately increased to add ? hysteresis ? to discourage the ic from switching back to continuous switching unless the load increases substantially. the ic returns to continuous switching as soon as an on- time is generated before the inductor current reaches zero. the on-time is reduced back to the length needed for 700khz switching and encouraging the circuit to remain in continuous conduction, preventing repetitive mode transitions between continuous switching and discontinuous switching. current limit the rt7275/76 current limit is a cycle-by-cycle ? valley ? type, measuring the inductor current through the synchronous rectifier during the off-time while the inductor current ramps down. the current is determined by measuring the voltage between source and drain of the synchronous rectifier, adding temperature compensation for greater accuracy. if the current exceeds the upper current limit, the on-time one-shot is inhibited until the inductor current ramps down below the upper current limit plus a wide hysteresis band of about 1a and drops below the lower current limit level. thus, only when the inductor current is well below the upper current limit is another on- time permitted. this arrangement prevents the average output current from greatly exceeding the guaranteed upper current limit value, as typically occurs with other valley-type current limits. if the output current exceeds the available inductor current (controlled by the current limit mechanism), the output voltage will drop. if it drops below the output under-voltage protection level (see next section) the ic will stop switching to avoid excessive heat. the rt7275 also includes a negative current limit to protect the ic against sinking excessive current and possibly damaging the ic. if the voltage across the synchronous rectifier indicates the negative current is too high, the synchronous rectifier turns off until after the next high- side on-time. the RT7276 does not sink current and therefore does not need a negative current limit. output over-voltage protection and under-voltage protection the rt7275/76 include output over-voltage protection (ovp). if the output voltage rises above the regulation level, the high-side switch naturally remains off and the synchronous rectifier turns on. if the output voltage remains high the synchronous rectifier remains on until the inductor current reaches the negative current limit (rt7275) or until it reaches zero (RT7276). if the output voltage remains high, the ic's switches remain off. if the output voltage exceeds the ovp trip threshold for longer than 5 s (typical), the ic's ovp is triggered. the rt7275/76 include output under-voltage protection (uvp). if the output voltage drops below the uvp trip threshold for longer than 250 s (typical) the ic's uvp is triggered. there are two different behaviors for ovp and uvp events, one for the wdfn-10l 3x3 packages and one for the tssop-14 (exposed pad) packages. ` hiccup mode (wdfn-10l 3x3 only) ` t he rt7275gqw/RT7276gqw, use hiccup mode ovp and uvp. when the protection function is triggered, the ic will shut down for a period of time and then attempt to recover automatically. hiccup mode allows the circuit to operate safely with low input current and power dissipation, and then resume normal operation as soon as the overload or short circuit is removed. during hiccup mode, the shutdown time is determined by the capacitor at ss. a 0.5 a current source discharges v ss from its starting voltage (normally v pvcc ). the ic remains shut down until v ss reaches 0.2v, about 40ms for a 3.9nf capacitor. at that point the ic begins to charge the ss capacitor at 2 a, and a normal start-up occurs. if the fault remains, ovp and uvp protection will be enabled when v ss reaches 2.2v (typical). the ic will then shut down and discharge the ss capacitor from the 2.2v level, taking about 17ms for a 3.9nf ss capacitor. free datasheet http:///
rt7275/76 13 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ` latch-off mode (tssop-14 (exposed pad) only) ` the rt7275gcp/RT7276gcp, use latch-off mode ovp and uvp. when the protection function is triggered the ic will shut down. the ic stops switching, leaving both switches open, and is latched off. to restart operation, toggle en or power the ic off and then on again. shut-down, start-up and enable (en) the enable input (en) has a logic-low level of 0.4v. when v en is below this level the ic enters shutdown mode and supply current drops to less than 10 a. when v en exceeds its logic-high level of 2v the ic is fully operational. between these 2 levels there are 2 thresholds (1.2v typical and 1.4v typical). when v en exceeds the lower threshold the internal bias regulators begin to function and supply current increases above the shutdown current level. switching operation begins when v en exceeds the upper threshold. unlike many competing devices, en is a high voltage input that can be safely connected to vin (up to 18v) for automatic start-up. input under-voltage lock-out in addition to the enable function, the rt7275/76 feature an under-voltage lock-out (uvlo) function that monitors the internal linear regulator output (pvcc). to prevent operation without fully-enhanced internal mosfet switches, this function inhibits switching when pvcc drops below the uvlo-falling threshold. the ic resumes switching when pvcc exceeds the uvlo-rising threshold. soft-start (ss) the rt7275/76 soft-start uses an external pin (ss) to clamp the output voltage and allow it to slowly rise. after v en is high and pvcc exceeds its uvlo threshold, the ic begins to source 2 a from the ss pin. an external capacitor at ss is used to adjust the soft-start timing. the available capacitance range is from 2.7nf to 220nf. do not leave ss unconnected. during start-up, while the ss capacitor charges, the rt7275/76 operate in discontinuous switching mode with very small pulses. this prevents negative inductor currents and keeps the circuit from sinking current. therefore, the output voltage may be pre-biased to some positive level before start-up. once the v ss ramp charges enough to raise the internal reference above the feedback voltage, switching will begin and the output voltage will smoothly rise from the pre-biased level to its regulated level. after v ss rises above about 2.2v output over-and under-voltage protections are enabled and the rt7275 begins continuous-switching operation. internal regulator (pvcc) an internal linear regulator (pvcc) produces a 5.1v supply from vin that powers the internal gate drivers, pwm logic, reference, analog circuitry, and other blocks. if vin is 6v or greater, pvcc is guaranteed to provide significant power for external loads. pgood comparator pgood is an open drain output controlled by a comparator connected to the feedback signal. if fb exceeds 90% of the internal reference voltage, pgood will be high impedance. otherwise, the pgood output is connected to pgnd. external bootstrap capacitor (c6) connect a 0.1 f low esr ceramic capacitor between boot and sw. this bootstrap capacitor provides the gate driver supply voltage for the high side n-channel mosfet switch. over temperature protection the rt7275/76 includes an over temperature protection (otp) circuitry to prevent overheating due to excessive power dissipation. the otp will shut down switching operation when the junction temperature exceeds 150 c. once the junction temperature cools down by approximately 20 c the ic will resume normal operation with a complete soft-start. for continuous operation, provide adequate cooling so that the junction temperature does not exceed 150 c. free datasheet http:///
rt7275/76 14 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit table 1. suggested component values (v in = 12v) v out (v) r1 (k ) r2 (k ) c3 (pf) l1 ( h) c7 ( f) 1 6.81 22.1 -- 1.4 22 to 68 1.05 8.25 22.1 -- 1.4 22 to 68 1.2 12.7 22.1 -- 1.4 22 to 68 1.8 30.1 22.1 5 to 22 2 22 to 68 2.5 49.9 22.1 5 to 22 2 22 to 68 3.3 73.2 22.1 5 to 22 2 22 to 68 5 124 22.1 5 to 22 3.3 22 to 68 7 180 22.1 5 to 22 3.3 22 to 68 rt7275/76 pvcc pgnd vin v in 10f x 2 c1 0.1f c2 ss 3.9nf c5 1f c4 v out 1.05v/3a gnd en input signal pgood output signal r3 100k pvcc boot l1 1.4h 0.1f c6 22f x 2 c7 sw 22k fb 8.25k r1 r2 c3 vout vinr free datasheet http:///
rt7275/76 15 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. design procedure inductor selection selecting an inductor involves specifying its inductance and also its required peak current. the exact inductor value is generally flexible and is ultimately chosen to obtain the best mix of cost, physical size, and circuit efficiency. lower inductor values benefit from reduced size and cost and they can improve the circuit's transient response, but they increase the inductor ripple current and output voltage ripple and reduce the efficiency due to the resulting higher peak currents. conversely, higher inductor values increase efficiency, but the inductor will either be physically larger or have higher resistance since more turns of wire are required and transient response will be slower since more time is required to change current (up or down) in the inductor. a good compromise between size, efficiency, and transient response is to use a ripple current ( i l ) about 20-50% of the desired full output load current. calculate the approximate inductor value by selecting the input and output voltages, the switching frequency (f sw ), the maximum output current (i out(max) ) and estimating a i l as some percentage of that current. ( ) ? out in out in sw l vvv l = vf i once an inductor value is chosen, the ripple current ( i l ) is calculated to determine the required peak inductor current. ( ) ? + out in out l l l(peak) out(max) in sw vvv i i = and i = i vf l 2 to guarantee the required output current, the inductor needs a saturation current rating and a thermal rating that exceeds i l(peak) . these are minimum requirements. to maintain control of inductor current in overload and short- circuit conditions, some applications may desire current ratings up to the current limit value. however, the ic's output under-voltage shutdown feature make this unnecessary for most applications. i l(peak) should not exceed the minimum value of ic's upper current limit level or the ic may not be able to meet the desired output current. if needed, reduce the inductor ripple current ( i l ) to increase the average inductor current (and the output current) while ensuring that i l(peak) does not exceed the upper current limit level. for best efficiency, choose an inductor with a low dc resistance that meets the cost and size requirements. for low inductor core losses some type of ferrite core is usually best and a shielded core type, although possibly larger or more expensive, will probably give fewer emi and other noise problems. considering the typical operating circuit for 1.05v output at 3a and an input voltage of 12v, using an inductor ripple of 1a (33%), the calculated inductance value is : ( ) ? 1.05v 12v 1.05v l = = 1.4 h 12v 700khz 1a the ripple current was selected at 1a and, as long as we use the calculated 1.4 h inductance, that should be the actual ripple current amount. typically the exact calculated inductance is not readily available and a nearby value is chosen. in this case 1.4 h was available and actually used in the typical circuit. to illustrate the next calculation, assume that for some reason is was necessary to select a 1.8 h inductor (for example). we would then calculate the ripple current and required peak current as below : ( ) ? l 1.05v 12v 1.05v i = = 0.76a 12v 700khz 1.8 h + l(peak) 0.76 and i = 3a = 3.38a 2 for the 1.8 h value, the inductor's saturation and thermal rating should exceed 3.38a. since the actual value used was 1.4 h and the ripple current exactly 1a, the required peak current is 3.5a. input capacitor selection the input filter capacitors are needed to smooth out the switched current drawn from the input power source and to reduce voltage ripple on the input. the actual capacitance value is less important than the rms current rating (and voltage rating, of course). the rms input ripple current (i rms ) is a function of the input voltage, output voltage, and load current : () ? out vin out rms out vin vvv i = i v ceramic capacitors are most often used because of their low cost, small size, high rms current ratings, and robust surge current capabilities. however, take care when these free datasheet http:///
rt7275/76 16 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. capacitors are used at the input of circuits supplied by a wall adapter or other supply connected through long, thin wires. current surges through the inductive wires can induce ringing at the rt7275/76's input which could potentially cause large, damaging voltage spikes at vin. if this phenomenon is observed, some bulk input capacitance may be required. ceramic capacitors (to meet the rms current requirement) can be placed in parallel with other types such as tantalum, electrolytic, or polymer (to reduce ringing and overshoot). choose capacitors rated at higher temperatures than required. several ceramic capacitors may be paralleled to meet the rms current, size, and height requirements of the application. the typical operating circuit uses two 10 f and one 0.1 f low esr ceramic capacitors on the input. output capacitor selection the rt7275/76 are optimized for ceramic output capacitors and best performance will be obtained using them. the total output capacitance value is usually determined by the desired output voltage ripple level and transient response requirements for sag (undershoot on positive load steps) and soar (overshoot on negative load steps). output ripple output ripple at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's esr and stored charge. these two ripple components are called esr ripple and capacitive ripple. since ceramic capacitors have extremely low esr and relatively little capacitance, both components are similar in amplitude and both should be considered if ripple is critical. + ripple ripple(esr) ripple(c) v = v v ? ripple(esr) l esr v = ir l ripple(c) out sw i v = 8c f for the typical operating circuit for 1.05v output and an inductor ripple of 1a, with 2 x 22 f output capacitance each with about 5m esr including pcb trace resistance, the output voltage ripple components are : ripple(esr) v = 1a 2.5m = 2.5mv ripple(c) 1a v= = 4mv 844 f0.7mhz ripple v = 2.5mv 4mv = 6.5mv + output transient undershoot and overshoot in addition to voltage ripple at the switching frequency, the output capacitor and its esr also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. the acot transient response is very quick and output transients are usually small. however, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and low duty cycle applications (which require high inductance to get reasonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. typically, load changes occur slowly with respect to the ic's 700khz switching frequency. but some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worst-case voltage swings in response to very fast load steps. the output voltage transient undershoot and overshoot each have two components : the voltage steps caused by the output capacitor's esr, and the voltage sag and soar due to the finite output capacitance and the inductor current slew rate. use the following formulas to check if the esr is low enough (typically not a problem with ceramic capacitors) and the output capacitance is large enough to prevent excessive sag and soar on very fast load step edges, with the chosen inductor value. the amplitude of the esr step up or down is a function of the load step and the esr of the output capacitor: ? esr_step out esr v = ir the amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle. the maximum duty cycle during a fast transient is a function of the on-time and the minimum off-time since the acot tm control scheme will ramp the current using on-times spaced apart with minimum off-times, which is free datasheet http:///
rt7275/76 17 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. as fast as allowed. calculate the approximate on-time (neglecting parasitics) and maximum duty cycle for a given input and output voltage as : + out on on max in sw on off(min) vt t = and d = vf t t the actual on-time will be slightly longer as the ic compensates for voltage drops in the circuit, but we can neglect both of these since the on-time increase compensates for the voltage losses. calculate the output voltage sag as : () ? 2 out sag out in(min) max out l(i ) v= 2c v d v the amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage : 2 out soar out out l(i ) v= 2c v for the typical operating circuit for 1.05v output, the circuit has an inductor 1.4 h and 2 x 22 f output capacitance with 5m esr each. the esr step is 3a x 2.5m = 7.5mv which is small, as expected. the output voltage sag and soar in response to full 0a-3a-0a instantaneous transients are : () ? 2 sag 1.4 h(3a) v = = 45mv 244 f 12v 0.35 1.05v on 1.05v t = = 125ns 12v 700khz 2 soar 1.4 h(3a) v = = 136mv 244 f1.05v the sag is about 4% of the output voltage and the soar is a full 13% of the output voltage. the esr step is negligible here but it does partially add to the soar, so keep that in mind whenever using higher-esr output capacitors. the soar is typically much worse than the sag in high- input, low-output step-down converters because the high input voltage demands a large inductor value which stores lots of energy that is all transferred into the output if the load stops drawing current. also, for a given inductor, the soar for a low output voltage is a greater voltage change + max 125ns and d = = 0.35 125ns 230ns and an even greater percentage of the output voltage. this is illustrated by comparing the previous to the next example. the typical operating circuit for 12v to 3.3v with a 2 h inductor and 2 x 22 f output capacitance can be used to illustrate the effect of a higher output voltag e. the output voltage sag and soar in response to full 0a-3a-0a instantaneous transients are calculated as follows : on 3.3v t = = 392ns 12v 700khz + max 392ns and d = = 0.63 392ns 230ns () ? 2 sag 2 h(3a) v = = 48mv 244 f 12v 0.63 3.3v 2 soar 2 h(3a) v = = 62mv 244 f3.3v in this case the sag is about 1.5% of the output voltage and the soar is only 2% of the output voltage. any sag is always short-lived, since the circuit quickly sources current to regain regulation in only a few switching cycles. with the rt7275, any overshoot transient is typically also short-lived since the converter will sink current, reversing the inductor current sharply until the output reaches regulation again. the RT7276's discontinuous operation at light loads prevents sinking current so, for that ic, the output voltage will soar until load current or leakage brings the voltage down to normal. most applications never experience instantaneous full load steps and the rt7275/76's high switching frequency and fast transient response can easily control voltage regulation at all times. also, since the sag and soar both are proportional to the square of the load change, if load steps were reduced to 1a (from the 3a examples preceding) the voltage changes would be reduced by a factor of almost ten. for these reasons sag and soar are seldom an issue except in very low-voltage cpu core or ddr memory supply applications, particularly for devices with high clock frequencies and quick changes into and out of sleep modes. in such applications, simply increasing the amount of ceramic output capacitor (sag and soar are directly proportional to capacitance) or adding extra bulk capacitance can easily eliminate any excessive voltage transients. free datasheet http:///
rt7275/76 18 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. in any application with large quick transients, always calculate soar to make sure that over-voltage protection will not be triggered. under-voltage is not likely since the threshold is very low (70%), that function has a long delay (250 s), and the ic will quickly return the output to regulation. over-voltage protection has a minimum threshold of 115% and short delay of 5 s and can actually be triggered by incorrect component choices, particularly for the RT7276 which does not sink current. output capacitors stability criteria the rt7275/76's acot tm control architecture uses an internal virtual inductor current ramp and other compensation that ensures stability with any reasonable output capacitor. the internal ramp allows the ic to operate with very low esr capacitors and the ic is stable with very small capacitances. therefore, output capacitor selection is nearly always a matter of meeting output voltage ripple and transient response requirements, as discussed in the previous sections. for the sake of the unusual application where ripple voltage is unimportant and there are few transients (perhaps battery charging or led lighting) the stability criteria are discussed below. the equations giving the minimum required capacitance for stable operation include a term that depends on the output capacitor's esr. the higher the esr, the lower the capacitance can be and still ensure stability. the equations can be greatly simplified if the esr term is removed by setting esr to zero. the resulting equation gives the worst-case minimum required capacitance and it is usually sufficiently small that there is usually no need for the more exact equation. the required output capacitance (c out ) is a function of the inductor value (l) and the input voltage (v in ) : ? 11 out in 5.23 10 c vl the worst-case high capacitance requirement is for low vin and small inductance, so a 5v to 3.3v converter is used for an example. using the inductance equation in a previous section to determine the required inductance : ( ) ? 3.3v 5v 3.3v l = = 1.6 h 5v 700khz 1a ? 11 out 5.23 10 c = 6.6 f 5v 1.6 h therefore, the required minimum capacitance for the 5v to 3.3v converter is : ? 11 out 5.24 10 c = 3.1 f 12v 1.4 h using the 12v to 1.05v typical application as another example : + out out sw in esr out v c 2 f v (r 13647 l v ) any esr in the output capacitor lowers the required minimum output capacitance, sometimes considerably. for the rare application where that is needed and useful, the equation including esr is given here : as can be seen, setting r esr to zero and simplifying the equation yields the previous simpler equation. to allow for the capacitor's temperature and bias voltage coefficients, use at least double the calculated capacitance and use a good quality dielectric such as x5r or x7r with an adequate voltage rating since ceramic capacitors exhibit considerable capacitance reduction as their bias voltage increases. feed-forward capacitor (c3) the rt7275/76 are optimized for ceramic output capacitors and for low duty cycle applications. this optimization makes circuit stability easy to achieve with reasonable output capacitors. however, the optimization affects the quality factor (q) of the circuit and therefore its transient response. to avoid an under-damped response (high q) and its potential ringing, the internal compensation was chosen to achieve perfect damping for low output voltages, where the fb divider has low attenuation (v out is close to v ref ). for high-output voltages, with high feedback attenuation, the circuit?s re sponse becomes over-damped and transient response can be slowed. in high-output voltage circuits (v out > 1.5v) transient response is improved by a dding a small ?feed-f orward? capa citor (c3) across the upper fb divider resistor, to increase the circuit's q and reduce damping to speed up the transient response without affecting the steady-state stability of the circuit. choose a capacitor value that gives, together with the divider impedance at fb, a time-constant between 100ns and 0.5 s. the divider impedance at fb is r1 in parallel with r2. c3 can be safely left out in low-output voltage circuits and if fast transient response is not required. free datasheet http:///
rt7275/76 19 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications information current-sinking applications (rt7275) the rt7275's is not recommended for current sinking applications even though its continuous switching operation allows the ic to sink some current. sinking enables a fast recovery from output voltage overshoot caused by load transients and is normally useful for applications requiring negative currents, such as ddr v tt bus termination applications and changing-output voltage applications where the output voltage needs to slew quickly from one voltage to another. however, the ic's negative current limit is set low (about 1.6a) and the current limit behavior latches the synchronous rectifier off until the high-side switch's next pulse, to prevent the possibility of ic damage from large negative currents. therefore, sinking current is not necessarily available at all times. if implementing applications where current-sinking may occur, take care to allow for the current that is delivered to the input supply. a step-down converter in sinking operation functions like a backwards step-up converter. the current that is sunk at its output terminals is delivered up to its input terminals. if this current has no outlet, the input voltage will rise. a good arrangement for long-term sinking applications is for a sinking supply (supply a) that is sinking current sourced from supply b, to both be powered by the same input supply. that way, any current delivered back to the input by supply a is current that just left the input through supply b. in this way, the current simply makes a round trip and the input supply will not rise. in cases where this is not possible, make sure that there are sufficient other loads on the input supply to prevent that supply's voltage from rising high enough to cause damage to itself or any of its loads. in cases where the sinking is not long-term, such as output-voltage slewing applications, make sure there is sufficient input capacitance to control any input voltage rise. the worst-case voltage rise is : out out in in cv v = c soft-start (ss) the rt7275/76 soft-start uses an external capacitor at ss to adjust the soft-start timing according to the following equation : ss ss ss c (nf)0.3v t(ms) = i ( a) the available capacitance range is from 2.7nf to 220nf. if a 3.9nf capacitor is used, the typical soft-start will be 0.6ms. do not leave ss unconnected. enable operation (en) for automatic start-up the high-voltage en pin can be connected to v in , either directly or through a 100k resistor. its large hysteresis band makes en useful for simple delay and timing circuits. en can be externally pulled to v in by adding a resistor-capacitor delay (r en and c en in figure 1). calculate the delay time using en's internal threshold where switching operation begins (1.4v, typical). an external mosfet can be added to implement digital control of en when no system voltage above 2v is available (figure 2). in this case, a 100k pull-up resistor, r en , is connected between vin and the en pin. mosfet q1 will be under logic control to pull down the en pin. to prevent enabling circuit when vin is smaller than the vout target value or some other desired voltage level, a resistive voltage divider can be placed between the input voltage and ground and connected to en to create an additional input under- voltage lockout threshold (figure 3). figure 1. external timing control figure 2. digital enable control circuit rt7275/76 en gnd 100k v in r en q1 enable rt7275/76 en gnd v in r en c en en free datasheet http:///
rt7275/76 20 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. resistor divider for lockout threshold setting output voltage setting set the desired output voltage using a resistive divider from the output to ground with the midpoint connected to fb. the output voltage is set according to the following equation : ) out r1 v = 0.765 (1 r2 + figure 4. output voltage setting place the fb resistors within 5mm of the fb pin. choose r2 between 10k and 100k to minimize power consumption without excessive noise pick-up and calculate r1 as follows : ? out r2 (v 0.765v) r1 = 0.765v for output voltage accuracy, use divider resistors with 1% or better tolerance. under voltage lockout protection the rt7275/76 feature an under-voltage lock-out (uvlo) function that monitors the internal linear regulator output (pvcc) and prevents operation if v pvcc is too low. in some multiple input voltage applications, it may be desirable to use a power input that is too low to allow v pvcc to exceed the uvlo threshold. in this case, if there is another low- power supply available that is high enough to operate the pvcc regulator, connecting that supply to vinr (tssop- 14 (exposed pad) only) will allow the ic to operate, using the lower-voltage high-power supply for the dc/dc power path. because of the internal linear regulator, any supply regulated or unregulated) between 4.5v and 18v will operate the ic. external boot bootstrap diode when the input voltage is lower than 5.5v it is recommended to add an external bootstrap diode between vin (or vinr) and the boot pin to improve enhancement of the internal mosfet switch and improve efficiency. the bootstrap diode can be a low cost one such as 1n4148 or bat54. figure 5. external bootstrap diode external boot capacitor series resistance the internal power mosfet switch gate driver is optimized to turn the switch on fast enough for low power loss and good efficiency, but also slow enough to reduce emi. switch turn-on is when most emi occurs since v sw rises rapidly. during switch turn-off, sw is discharged relatively slowly by the inductor current during the dead- time between high-side and low-side switch on-times. in some cases it is desirable to reduce emi further, at the expense of some additional power dissipation. the switch turn-on can be slowed by placing a small (<10 ) resistance between boot and the external bootstrap capacitor. this will slow the high-side switch turn-on and v sw 's rise. to remove the resistor from the capacitor charging path (avoiding poor enhancement due to under- charging the boot capacitor), use the external diode shown in figure 5 to charge the boot capacitor and place the resistance between boot and the capacitor/diode connection. pvcc capacitor selection decouple pvcc to pgnd with a 1 f ceramic capacitor. high grade dielectric (x7r, or x5r) ceramic capacitors are recommended for their stable temperature and bias voltage characteristics. rt7275/76 en gnd v in r en1 r en2 rt7275/76 gnd fb r1 r2 v out sw boot 5v 0.1f rt7275/76 free datasheet http:///
rt7275/76 21 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. thermal considerations the maximum power dissipation depends on the thermal resistance of the ic package and the pcb layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for the tssop-14 (exposed pad) package the thermal resistance, ja , is 40 c/w on a standard jedec 51-7 four-layer thermal test board. for the wdfn-10l 3x3 package the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. these standard thermal test layouts have a very large area with long 2oz. copper traces connected to each ic pin and very large, unbroken 1oz. internal power and ground planes. meeting the performance of the standard thermal test board in a typical tiny board area requires wide copper traces well-connected to the ic's backside pad leading to exposed copper areas on the component side of the board as well as good thermal vias from the backside pad connecting to a wide inner-layer ground plane and, perhaps, to an exposed copper area on the board's solder side. using the backside tab in this way, 40 c/w is achievable in a small area with either package. the maximum power dissipation at t a = 25 c can be calculated by the following formulas: p d(max) = (125 c ? 25 c) / (40 c/w) = 2.50w for tssop-14 (exposed pad) package p d(max) = (125 c ? 25 c) / (60 c/w) = 1.67w for wdfn-10l 3x3 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb wdfn-10l3x3 tssop-14 (exposed pad) layout considerations follow the pcb layout guidelines for optimal performance of the rt7275/76. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and pgnd). ` the high-frequency switching node (sw) has large voltage swings and fast edges and can easily radiate noise to adjacent components. keep its area small to prevent excessive emi, while providing wide copper traces to minimize parasitic resistance and inductance. keep sensitive components away from the sw node or provide ground traces between for shielding, to prevent stray capacitive noise pickup. ` connect the feedback network to the output capacitors rather than the inductor. place the feedback components near the fb pin. ` the exposed pad, pgnd, and gnd should be connected to large copper areas for heat sinking and noise protection. provide dedicated wide copper traces for the power path ground between the ic and the input and output capacitor grounds, rather than connecting each of these individually to an internal ground plane. ` avoid using vias in the power path connections that have switched currents (from c in to pgnd and c in to vin) and the switching node (sw). free datasheet http:///
rt7275/76 22 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7. pcb layout guide (a). for tssop-14 (exposed pad) package c in l v out v out c vcc r2 r1 pgnd sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. en fb pgood ss vin vin boot sw sw pvcc 9 8 7 1 2 3 4 5 10 6 pgnd 11 c boot c out pgnd place the feedback components as close to the fb as possible for better regulation. place the input and output capacitors as close to the ic as possible. fb vin pgnd gnd ss pvcc pgood en pgnd sw sw boot vout vinr 4 2 3 5 7 6 11 13 12 10 8 9 14 pgnd 15 r2 r1 c vcc c in c boot l v out c out sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. place the feedback components as close to the fb as possible for better regulation. place the input and output capacitors as close to the ic as possible. v out pgnd (b). for wdfn-10l 3x3 package free datasheet http:///
rt7275/76 23 ds7275/76-00 january 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 1.000 1.200 0.039 0.047 a1 0.000 0.150 0.000 0.006 a2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 d 4.900 5.100 0.193 0.201 e 0.650 0.026 e 6.300 6.500 0.248 0.256 e1 4.300 4.500 0.169 0.177 l 0.450 0.750 0.018 0.030 u 1.900 2.900 0.075 0.114 v 1.600 2.600 0.063 0.102 14-lead tssop (exposed pad) plastic package free datasheet http:///
rt7275/76 24 ds7275/76-00 january 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a free datasheet http:///

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